1. Field of the Invention
The present invention relates generally to a data process circuit for processing a data selectively in two different byte length and, more particularly, to a memory system accessible in 2.sup.n (n is an integer) bits as well as in 2.sup.m (m is an integer satisfying the condition of m&gt;n) bits.
2. Description of the Prior Art
With evolution of the microcomputers, the number of bits constituting the data of the microcomputer is increased from 4 bits to 8 bits and from 8 bits to 16 bits. Specifically, 16-bit microcomputers have become widely used in such industrial field and in consumer field in which mainly 8-bit microcomputers were conventionally used, due to the strong demand for high operation performance. Commonly, an EPROM (Electrically Programmable Read Only Memory) for storing a user program suitable for its application is provided in a microcomputer, and an EPROM of 8 bit structure is generally used.
FIG. 1 shows one example of a system employing a conventional 8 bit EPROM and a 16 bit CPU. Referring to FIG. 1, the system comprises a 16 bit CPU (Central Processing Unit) 1 such as M37790 by Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan, two 8 bit EPROMs 2 and 3, that is, an EPROM 2 for the even-numbered address (less significant address) and an EPROM 3 for odd-numbered address (more significant address). Each EPROM is, for example, a product of No. 27128 by Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan.
The CPU 1 comprises an address terminal 51 for outputting 15 bit address signals A0 to A14, an input/output terminal 52 for the low-order (less significant) 8 bits data D0 to D7, an input/output terminal 54 for inputting and outputting the high-order (more significant) 8 bit data and a BHE terminal 53 for outputting a signal BHE designating the access to the high-order data of the odd-numbered address.
The EPROM 2 for the even-numbered address comprises an address input terminal 61 for receiving 14 bit address signals A1 to A14 out of 15 bit address signals A0 to A14 from the CPU 1, an output enable terminal 62 for receiving the least significant address signal A0 from the CPU 1, a data output terminal 63 for outputting 8 bit data D0 to D7 and a chip enable terminal 64 connected to the ground. Since the EPROM 2 is has its chip enable terminal 64 connected to the ground, it is always in the active state (enabled state). When a "L" signal is applied to the output enable terminal 62, the EPROM 2 is enabled to output from the terminal 63 a data stored in an address corresponding to that applied to the address input terminal 61.
The EPROM 3 for the odd-numbered address comprises an address input terminal 71 for receiving 14 bit address signals A1 to A14 from the CPU 1, an output enable terminal 72 for receiving the odd-numbered address access designating signal BHE from the CPU 1, a data output terminal 73 for outputting 8 bit data D0 to D7 in addresses corresponding to the address signals applied to the address input terminal 71 and a chip enable terminal 74 connected to the ground potential. Since the chip enable terminal 74 is connected to the ground potential, the EPROM 3 is always in the enabled state. When the byte high enable signal (odd-numbered address access designating signal) BHE applied to the output enable terminal 72 is "L", the EPROM 3 is enabled to output from the data output terminal 73 the content in the address designated by the address signals A1 to A14 applied to the address input terminal 71.
The 15 bit address signals A0 to A14 from the CPU 1 are sent onto a 15 bit address bus 4. The 8 bit data D0 to D7 from the EPROM 2 are applied to the low-order data input/output terminal 52 of the CPU 1 through a low-order 8 bit data bus 5. The 8 bit data from the EPROM 3 are applied to the high-order 8 bit data input/output terminal 54 of the CPU 1 through a high-order 8 bit data bus 6.
The selection of the even-numbered address and the odd-numbered address is carried out by the least significant address signal A0. Namely, when the address signal A0 is "0" ("L"), an even-numbered address is designated, and when the least significant address signal A0 is "1" ("H"), an odd-numbered address is designated.
When the byte high enable BHE signal is "L", it designates an access to an odd-numbered address and, when it is "H", it inhibits an access to the odd-numbered address.
FIG. 2 is a waveform diagram showing the data reading operation in a conventional structure employing a 16 bit CPU and a 8 bit EPROM. The operation will be hereinafter described with reference to the FIGS. 1 and 2.
Most of the CPUs having a 16 bit data bus are capable of simultaneously accessing successive even-numbered address and odd-numbered address for the two EPROMs 2 and 3 in the same CPU cycle. Description will be made of an operation in which the CPU 1 accesses the EPROMs 2 and 3 in 16 bits. First, even-numbered address signals A0 to A14 appear on the address bus 4. More specifically, the least significant address signal A0 is at "L" level. Thereafter, the BHE signal becomes "L" level and the address signals applied to the address bus 4 are drawn into each of the EPROMs 2 and 3. The least significant address signal A0 is applied to the output enable terminal 62 of the EPROM 2 for the even numbered address while the BHE signal is applied to the output enable terminal 72 of the EPROM 3 for the odd-numbered address. Therefore, both EPROMs 2 and 3 simultaneously enter the output enable state to output data in the addresses designated by the address signals A1 to A14. Since the address signals A1 to A14 are common to both of the EPROMs 2 and 3, the data outputted from both EPROMs 2 and 3 become a continuous 2 byte data comprising an even-numbered address and a following odd-numbered address. The data from the EPROM 2 for the even-numbered address is applied to the low-order data bus 5 through the data output terminal 63 while the 8 bit data from the EPROM 3 for the odd-numbered address is applied to the high-order data bus 6 from the data output terminal 73. The CPU 1 receives simultaneously the continuous 2 byte data through the low-order data bus 5 and the high-order data bus 6. The CPU 1 repeats the above described operation of reading the 16 bit data from the EPROMs 2 and 3, where necessary in view of the content to be processed.
Depending on the content to be processed, sometimes the CPU 1 requires only the byte unit (8 bit) data. In such case, only one of the least significant signal A0 and the BHE signal is made active ("L" level) for accessing the EPROM 2 or 3. Namely, in accessing the EPROM 3 for the odd-numbered address, the least significant address signal A0 is made "1" ("H") and the BHE signal is made "L". On this occasion, a "H" signal is applied to the output enable terminal 62 of the EPROM 2 for the even-numbered address, so that the EPROM 2 becomes output disabled state. Meanwhile, since an "L" signal is applied to the output enable terminal 72 of the EPROM 3 for the odd-numbered address, the EPROM 3 becomes output enabled state and it outputs, on the high-order data bus 6, 8 bit data in an address corresponding to the address signals A1 to A14 applied from the CPU 1. As a result, an 8 bit data from the odd-numbered addresses is read out.
In accessing the EPROM 2 for the even-numbered address only, the least significant address signal A0 is made "0" ("L" level) and the BHE signal is made "H". Therefore, the EPROM 3 for the odd-numbered address becomes output disabled state while the EPROM 2 for the even-numbered address becomes output enabled state and the EPROM 2 outputs, on the low-order data bus 5, 8 bit data in address corresponding to the address signals A1 to A14 applied through the address bus 4.
In either operation, namely, in accessing in unit of 8 bits or in accessing in unit of 16 bits, data stored in an even-numbered address appears on the low-order data bus 5 while data stored in an odd-numbered address appears on the high-order data bus 6.
The system can be constituted by a 16 bit EPROM instead of the above described two 8-bit EPROMs.
FIG. 3 shows a conventional connection between the CPU and EPROM in a system employing a 16 bit EPROM.
Referring to FIG. 3 the 16 bit CPU 1 comprises an address output terminal 55 for outputting 15 bit address signals A0 to A14, a data input/output terminal 56 for inputting and outputting the low order 8 bit data D0 to D7, a data input/output terminal 57 for inputting and outputting the high-order 8 bit data D8 to D15, an enable terminal 58 for outputting an enable signal E for activating the memory and a terminal 59 for outputting read/write signal R/W designating the writing/reading operation of the memory.
The 16 bit EPROM 2a comprises an address input terminal 65 for receiving 14 bit address signals A1 to A14, the data output terminal 66 for outputting the low-order 8 bit data D0 to D7, a data output terminal 67 for outputting the high order 8 bit data D8 to D15, a chip enable terminal 68 for receiving an enable signal E from the CPU 1 and an output enable terminal 69 for inverting and receiving the read/write signal R/W from the CPU 1. When a "L" signal is applied to the chip enable terminal 68, the EPROM 2a becomes the enabled state and when a "L" signal is applied to the output enable terminal 69, it becomes the output enable state.
FIG. 4 is a waveform diagram showing the data reading operation of a case in which the 16-bit word EPROM shown in FIG. 3 is employed. The data reading operation with a conventional 16 bit EPROM employed will be described with reference to the FIGS. 3 and 4.
Address signals A0 to A14 are supplied onto the address bus 4 from the CPU 1. Then the enable signal E from the CPU 1 falls so that the EPROM 2a enters the enabled state and it takes the 14 bit address signals A1 to A14 on the address bus 4 in and outputs data in address corresponding to the supplied address signals. On this occasion, the read/write signal R/W is "H" for the reading operation and a "L" signal is applied to the output enable terminal 69. Therefore, the EPROM 2a enters output enable state and the 16 bit data stored in the address corresponding to the supplied address signals A1 to A14 is transferred onto the data buses 5 and 6. The CPU 1 receives the low-order 8 bit data read out onto the data bus 5 through a low-order 8 bit data input terminal 50. Meanwhile, the high-order 8 bit data D8 to D15 are supplied to the high-order data input terminal 57 of the CPU 1 through the high-order data bus 6. On this occasion, the EPROM 2a sends out the content in the address corresponding to the supplied address signals A1 to A14, so that 8 bit information in an even numbered address and 8 bit information of the odd numbered address following the accessed even numbered address are simultaneously read out.
Other than the above described structure employing the EPROM, the CPU comprises a random access memory for storing data and the like. In this case, 16-bit random access memory is employed. This random access memory (RAM) has even-numbered addresses and odd-numbered addresses for storing data of a byte size, respectively, and the word size (16 bit) data is constituted by data in successive even-numbered address and odd-numbered address data. In this case also, the data of the even-numbered address is outputted to the low-order 8 bit data bus while the data of the odd-numbered address is outputted to the high-order 8 bit data bus. Namely, it should be understood that the EPROM of FIG. 3 is replaced by the RAM.
FIG. 5 shows a relation between the address and the data bus when a conventional 8 bit memory or 16 bit memory is connected to a CPU having a 16 bit data bus. As can be seen from FIG. 5, either in the 8 bit memory or in the 16 bit memory, the address is designated by the address signals A1 to A14, so that the address N (N is an integer) and address N+1 are simultaneously accessed. More specifically, an even-numbered address and the successive odd-numbered address are designated by the address signals A1 to A14. At this time, the data in the even-numbered address appears on the low-order data bus while the data in the odd-numbered address appears on the high-order data bus.
Generally, a CPU has a register for storing data, program and the like. As for the register in the CPU, the register connected to the high-order data bus and the register connected to the low-order data bus are fixed. Namely, as shown in FIG. 6, the register B is connected to the high-order data bus and therefore connected to the odd-numbered address of the memory while the register A is connected to the even-numbered address through the low-order data bus. This structure brings about some problems as to be described in the following. Namely, depending on the content of the processing by the CPU, there is a case in which only the high-order 8 bit data is required and not the low-order 8 bit. In other words, there is a case in which 8 bit data from the odd-numbered address only is needed. Since the CPU is commonly structured such that the register A is accessed earlier, in such case the content in the register B should be once transferred to the register A to be read. In such case, a register exchange instruction such as "XCH" is prepared to exchange the contents of the register B and register A. However, when the content in the register B is transferred to the register A, in a common structure, the content is transferred in bit-by-bit shifting. Therefore, the exchange takes much time and therefore there arises another problem that desired arithmetical processing and data processing are not carried out at high speed. More specifically, when a certain processing is desired using 8 bit data only of the odd-numbered address, the 8 bit data is always stored in the high-order register B, so that the data should be once transferred to the register A. Consequently, the processing using the data of the odd-numbered address can not be carried out at high speed. This problem will be described more specifically, in the following, with reference to FIGS. 7 through 9. Now, discussed is a case where a certain operation is performed on each 8-bit data stored in two 8-bit memories, and a resultant data is again stored in original memory location by a 16-bit CPU, in a memory system as shown in FIG. 7. In FIG. 7, the memory system includes a 16-bit CPU 500, a memory 510 for storing 8-bit data of odd-numbered address and a memory 520 for storing 8-bit data of even-numbered address. The memory 510 is connected through an eight bit data bus 511 to a high-order byte data bus DBH. The memory 520 is connected through an 8-bit data bus 512 to a low-order data bus DBL. The 16-bit CPU 500 receives and transmits data of odd-numbered addresses from/to the data bus DBH and data of even-numbered addresses from/to the data bus DBL. The memory mapping or memory locations of the memory system of FIG. 7 is shown in FIG. 8. A program employed in the process is shown in FIG. 9A, as an example. FIG. 9B represents operational significance of each step in the program, and FIG. 9C shows the content in a 16-bit register A provided in the CPU 500 after completion of corresponding program step. It should be noted that the 16-bit register A is what is different from the 8-bit register A shown in FIG. 6.
When the CPU performs 8-bit data processing, it first accesses to both memories 510 and 520 to load the accessed 16 bit data in the 16-bit register A with the data of odd-numbered address and the data of even-numbered address stored in high-order 8-bit position and low-order 8-bit position in the register A, respectively. Then, low byte data is processed by the CPU 500 to provide a result a, since only low byte data in the register A can be processed in 8-bit processing mode. Byte swap operation is performed, and the content of the register A is once saved in the original locations of the memories 510 and 520. Again, the same sequence as that described above is performed to store the result a (first result) and the result b (second result) in the original locations of respective memories 510 and 520. As explicitly shown in FIGS. 9A to 9C, byte swapping operation of "RLA #8" is executed several times. This byte swapping is performed by shifting the data in the register A bit by bit, and it requires much time. In addition, when the program forms a looped routine, the time required in the byte swapping process is accumulated to prevent fast completion of the program.
Further, there is another problem that the contents in the 8-bit register A (or low byte register) can not be saved in the odd-numbered address, i.e., high byte data memory.
In addition, when a 16-bit EPROM is constituted by two EPROMs which can process 8 bit data only, EPROMs for the even-numbered address and for the odd-numbered address must be used in a pair. In such case, when a wrong EPROM is taken for the pair, or the assembling position of the pair of EPROMs is inverted, the data stored in the pair of EPROMs have no continuity. Consequently, the address signals generated by the CPU do not correspond to the stored content, so that the system including the CPU and memory do not operate correctly. The reason for this is that a 8-bit PROM writer is usually used for programming the 8-bit EPROM and the programming of EPROMs is carried out one by one so that the program for the even-numbered address and the program for the odd-numbered address should be separately made in the two EPROMs, respectively. Further, in a multi CPU system having an additional 8-bit CPU 600 coupled to the low byte data bus DBL, as shown in FIG. 10, the 8-bit CPU 600 can not access the memory for storing 8-bit data of odd-numbered addresses. That is, referring to FIG. 11 representing the memory mapping for the multi CPU system of FIG. 10, the 8-bit CPU 600 can not perform any operation on data of odd-numbered addresses N+i (N=2n, i=1, 2, . . . ) shown by hatched regions in FIG. 10, which degrades the performance of a multi CPU system with at least one CPU processing data of different bit length.